♦ Dual high-performance and low-power ARM Cortex-A9 MP Core processor
♦ Full implementation of the ARM v7-A architecture and command system, ARM NEON Advanced SIMD support (one instruction, a lot of data) for accelerated signal processing and other media calculations
♦ Superscalar, variable length, with extraordinary execution of the conveyor with the module of dynamic prediction of conditional transitions, 8 levels of the conveyor
♦ Includes VFPv3 hardware for addition, subtraction, division, multiplication, and square root with single and double precision
♦ SCU provides memory alignment between two cores.
♦ Separate timer and watchdog timer for each core
♦ 32 KB cache of instructions of the first level, 32 KB cache of data of the first level with 4-fold associativity
♦ 512 KB combined (instructions + data) second-level cache
♦ Trustzone technology support
♦ Complete ARM CoreSight debug system:
в—Џ Availability for debugging and tracing of whole systems
в—Џ ETM trace support
в—Џ Aggressive (invasive) and non-invasive (non-invasive) debugging
♦ Four separate power domains with support for internal power switching to the cores and processor units and external on / off switching, depending on the scenario selected by the application:
в—Џ PD_A9_0: First Cortex-A9 Core + Neon + FPU + L1 instruction and data cache
в—Џ PD_A9_1: Second core Cortex-A9 + Neon + FPU + L1 instruction cache and data
в—Џ PD_DBG: CoreSight-DK for Cortex A9
в—Џ PD_SCU: SCU + L2 Cache
♦ One isolated power domain to support DVFS
♦ The maximum frequency of the processor in the worst case is 750 MHz with a core voltage of 1.0 V, the normal one is 1.1 GHz with a core voltage of 1.1 V, and a maximum of 1.5 GHz.

♦ Built-in memory
в—Џ 10 KB BootROM (boot flash)
в—Џ 64 KB of integrated SRAM for secure and non-secure access. The size of the protected and unprotected area is set by software.
в—Џ 256 KB or 512 KB embedded SRAM together with a second-level cache
♦ External memory
в—Џ DDR3-800, 16/32 bit data width, 2 ranks, a total of 2 GB (maximum) address space, for one rank also a maximum address space of 2 GB
в—Џ LPDDR-400, 32 bit data width, 2 ranks, only 2 GB (maximum) of address space, for one rank also a maximum address space of 2 GB
в—Џ LPDDR2-800, 32-bit data width, 2 ranks, a total of 2 GB (maximum) address space, for one rank also a maximum address space of 2 GB
в—Џ Asynchronous SRAM / NOR Flash, 8/16 bit data width, 2 banks, 1 MB (maximum) address space per bank
в—Џ Asynchronous NAND Flash (including LBA NAND), 8/16 bit data width, 8 banks, 60 bits ECC
в—Џ ONFI NAND Flash synchronous, 8-bit data width, 8 banks, 60 bits ECC

♦ Built-in BootROM (boot flash)
в—Џ Size: 10 KB
в—Џ Supports system boot from the following devices:
в–  8/16 bit asynchronous NAND Flash
в–  8 bit ONFI NAND Flash
в–  SPI0 interface
в–  eMMC interface
в—Џ Support for loading system code through the following interfaces:
в–  USB OTG interface
в–  UART0 interface
♦ Built-in SRAM
в—Џ Size: 64 KB
в—Џ Support secure and non-secure access
в—Џ The size of the protected and non-protected area is set by software.
в—Џ A protected area can be 0 KB, 4 KB, 8 KB, 12 KB, 16 KB, ..., 60 KB, 64 KB
♦ 256 KB or 512 KB built-in SRAM together with a second-level cache for Cortex-A9, the size is set by software

♦ Dynamic Memory Interface (DDR3 / LPDDR / LPDDR2)
в—Џ Compliant with JEDEC DDR3 / LPDDR / LPDDR2 SDRAM standard
в—Џ Data rates up to 800 Mbps (400 MHz) for DDR3 / LPDDR2 and up to 400 Mbps (200 MHz) for LPDDR
● Supports up to 2 ranks of memory (CS signals — chip selection), 2 GB (total) of the address space and up to a maximum of 2 GB of address space per rank, which is software configured
в—Џ 16 bits / 32 bits data bus width is set by software
в—Џ 5 host ports with 64-bit AXI bus interface for system access, AXI bus frequency asynchronous with DDR clock frequency
в—Џ Programmable timing parameters to support DDR3 / LPDDR / LPDDR2 SDRAM from various manufacturers
в—Џ Advanced scheduling and command swapping for maximum bus utilization.
в—Џ Low power modes, such as power off and self-updating for DDR3 / LPDDR / LPDDR2; LPDDR / LPDDR2 SDRAM stop clocking and deep power down
в—Џ Compensation of time delays caused by circuit designs and variable delays through programmable conveyors
в—Џ Built-in dynamic frequency drift detector in PHY to compensate for these deviations by the controller
в—Џ Programmable output and ODT impedance with PVT dynamic compensation
в—Џ Support for one power-saving mode: powering off the DDR PHY and most DDR I / O signals, with the exception of two CS and two CKE output signals, SDRAM runs in self-refresh mode to prevent data loss
♦ Static memory interface (ASRAM / Nor Flash)
в—Џ Compatible with standard asynchronous SRAM or Nor Flash
в—Џ Supports up to two banks (CS - chip select signals), maximum 1MB of address space per bank
в—Џ For Bank 0, the data bus width is set by software at 8 bits / 16 bits, for Bank 1, the data bus width is fixed at 16 bits
в—Џ Support for individual data bus lines and address bus, as well as support for data bus multiplex mode and address bus for keeping free I / O lines
♦ NAND Flash Interface
в—Џ Supports 8 bit / 16 bit asynchronous NAND flash, up to 8 banks
в—Џ Supports 8 bit synchronous DDR NAND flash, up to 8 banks
в—Џ LBA NAND flash support in asynchronous or synchronous mode
в—Џ Hardware ECC up to 60 bits
в—Џ For DDR NAND Flash, 1/4 or 1/8 frequency dividers are supported, the maximum operating frequency is 75 MHz
в—Џ For asynchronous NAND flash, configurable time settings supported, maximum data transfer rate of 16 bits / cycle
в—Џ Built-in dedicated DMA data interface
в—Џ Data transfer along with the main DMAC1 in the SoC system is also supported.
♦ eMMC Interface
в—Џ Compatible with standard iNAND interface
в—Џ MMC 4.41 protocol support
в—Џ Provides a sequence of boot commands for external eMMC devices
в—Џ Supports one combined FIFO (32 x 32 bits) for data transmission and reception
в—Џ Support to prevent overflow and emptying of the FIFO by automatically stopping the card clocking
в—Џ Support CRC generation and error detection
в—Џ Host support of control signals for card detection and initialization, as well as for write protection
в—Џ Internal frequency divider for software data rate control
в—Џ Block size support from 1 to 65535 bytes
в—Џ 8-bit data bus width
♦ SD / MMC interface
в—Џ Compatible with SD 3.0, MMC 4.41
в—Џ Supports one combined FIFO (32 x 32 bits) for data transmission and reception
в—Џ Support to prevent overflow and emptying of the FIFO by automatically stopping the card clocking
в—Џ Support CRC generation and error detection
в—Џ Host support of control signals for card detection and initialization, as well as for write protection
в—Џ Internal frequency divider for software data rate control
в—Џ Block size support from 1 to 65535 bytes
в—Џ The data bus width is flexible to support 1 bit / 4 bit for SD mode and 1 bit / 4 bit / 8 bit for MMC mode

♦ CRU (clocking and reset module)
в—Џ Support individual clocking of all components within RK3066
в—Џ Support of reset management both of the entire SoC at once, and individually of each component separately.
в—Џ Supports flexible frequency setting, including various frequency sources, frequency multiplexers and frequency dividers
в—Џ Up to 1.5 GHz output frequency for all PLL
в—Џ One 24 MHz frequency generator and 4 onboard PLLs
♦ PMU (power management module)
в—Џ 7 modes of operation (slow mode, normal mode, standby mode, deep standby mode, stop mode, sleep mode, power off mode) to save power using different operating frequencies or individual clocking of internal modules or power on / off
в—Џ Many sources of awakening in different modes
в—Џ 9 separate power domains with software on / off for various applications
♦ Timers
в—Џ 3 built-in 32 bit timers with interrupt support
в—Џ Support two modes of operation: free start and user account
в—Џ Support for monitoring timer operation status
в—Џ Fixed input frequency 24 MHz
♦ PWM (pulse width modulators)
в—Џ 4 built-in pulse width modulators with interrupt support
в—Џ Programmable 4-bit scaling factor from the bus APB frequency
в—Џ Built-in 32 bit timer / counter feature
в—Џ Supports single trigger or continuous pulse width modulation
в—Џ Masked interrupt support
в—Џ Provides a reference mode and output signal of various duty cycle
в—Џ Provides a mode of capture and measurement of the duty cycle of the input signal
♦ Watchdog Timer (WDT)
в—Џ 32 bits
в—Џ The clock frequency of the meter is taken from the APB bus
в—Џ The counter counts from the set value to 0, to indicate the timeout
в—Џ WDT can perform two kinds of operations when a timeout occurs:
в–  Generate system reset
в–  First generate an interrupt and if the interrupt handler does not clear the flag, then during the second timeout, generate a system reset
в—Џ Programmable reset pulse duration
в—Џ Total 16 defined timeout period ranges
♦ Bus architecture
в—Џ 64-bit multi-layer AXI / AHB / APB composite bus architecture
в—Џ Five built-in AXI connections:
в–  The central processor is connected to three 64-bit AXI master, two 64-bit AXI slave, one 32-bit AHB master and a set of 32-bit AHB / APB slave
в–  Peripheral modules are connected to two 64-bit AXI master, one 64-bit AXI slave, one 32-bit AXI slave, four 32-bit AHB master and a set of 32-bit AHB / APB slave
в–  The display is connected to six 64-bit AXI master and one 32-bit AHB slave
в–  The graphics processor is connected to one 128-bit AXI master and one 32-bit APB slave, they are a type of point-to-point AXI-Lite architecture
в–  VCODEC (video encoder / decoder) is also connected to one 64-bit AXI master and one 32-bit AHB slave, they are point-to-point AXI-Lite architecture
в—Џ For each connection to the AXI / AHB / APB bus, the clock frequency for the AXI / AHB / APB domains is always synchronous, and various integer dividers are supported for it
в—Џ Various flexible solutions based on QoS algorithms to improve bus bandwidth
♦ Interrupt Controller
в—Џ Supports 3 interrupt sources of PPI type (Private Peripheral Interrupt) and 76 sources of SPI type (Shared Peripheral Interrupt) incoming from various components inside RK3066
в—Џ Support 16 software interrupts
в—Џ The input interrupt level is fixed and always high.
в—Џ Two output interrupts (nFIQ and n IRQ) per core Cortex-A9, both active low
в—Џ Support for different priorities for each interrupt source, configurable by software
♦ DMA controller (DMAC)
в—Џ DMA is based on micro code programs.
в—Џ Special instruction set provides flexibility for programming DMA data transfers
в—Џ DMA function list fully supports fragmented input / output (scatter / gather I / O)
в—Џ Support for internal instruction cache
в—Џ Built-in DMA control flow
в—Џ Supports data transfer from memory to memory, from memory to peripheral units, from peripheral units to memory
в—Џ Signals the occurrence of various DMA events using interrupt output signals
в—Џ Comparison of the relationship of each channel and different interrupt outputs is configured by software
в—Џ Two onboard DMA controllers, DMAC0 for CPU and DMAC1 for peripheral systems
в—Џ DMAC0 features:
в–  6 channels in total
в–  11 hardware requests from peripheral systems
в–  2 output interrupts
в–  Dual APB slave interface for register configuration, defined as protected and unprotected
в–  Support for TrustZone technology and protected state for each DMA channel programmatically specified
в—Џ DMAC1 features:
в–  only 7 channels
в–  13 hardware requests from peripheral systems
в–  2 output interrupts
в–  Does not support TrustZone technology
♦ Protection system
в—Џ Support TrustZone technology for the following components inside the RK3066:
в–  Cortex-A9 - support for protected and unprotected mode, switches by software
в–  DMAC0 - support several specialized channels working only in protected mode
в–  eFuse - only Cortex-A9 is available in protected mode
в–  Built-in memory - part of the space is addressed only in protected mode, the detailed size is set programmatically together with TZMA (TrustZone memory adapter) and TZPC (TrustZone protection controller)

♦ Shared internal memory and interface with bus for video decoder and encoder
♦ Video Decoder
в—Џ Real-time video decoding of MPEG-1, MPEG-2, MPEG-4, H.263, H.264, AVS, VC-1, RV, VP6 / VP8, Sorenson Spark, MVC
в—Џ Supports error detection and masking for all video formats.
в—Џ YUV420 output data formats are semi-planar, and YUV400 (monochrome) are also supported for H.264
в—Џ H.264 to HP 4.2 level: 1080p @ 60fps (1920 Г— 1010)
в—Џ MPEG-4 to ASP level 5: 1080p @ 60fps (1920 Г— 1010)
в—Џ MPEG-2 to MP: 1080p @ 60fps (1920 Г— 1010)
в—Џ MPEG-1 to MP: 1080p @ 60fps (1920 Г— 1010)
в—Џ H.263: 576p @ 60fps (720CH576)
в—Џ Sorenson Spark: 1080p @ 60fps (1920 Г— 1010)
в—Џ VC-1 up to AP level 3: 1080p @ 30fps (1920 Г— 1010)
в—Џ RV8 / RV9 / RV10: 1080p @ 60fps (1920 Г— 1088)
в—Џ VP6 / VP8: 1080p @ 60fps (1920 Г— 1088)
в—Џ AVS: 1080p @ 60fps (1920 Г— 1088)
в—Џ MVC: 1080p @ 60fps (1920 Г— 1088)
в—Џ For AVS, 4: 4: 4 sampling is not supported.
в—Џ For H.264, image cropping is not supported
в—Џ For MPEG-4, GMC is not supported.
в—Џ For VC-1, scaling and range display are supported in the postprocessor image
в—Џ For MPEG-4 SP / H.263 / Sorenson spark, a modified H.264 loop filter is used to implement a deblocking filter in the postprocessor module
♦ Video Coder
в—Џ Video encoder support for H.264 ([email protected], [email protected], [email protected]), MVC and VP8
в—Џ Support only I and P layers, B layers are not supported
в—Џ Supports error tolerance based on limited intra prediction and layers
в—Џ Input Formats:
в–  YCbCr 4: 2: 0 planar
в–  YCbCr 4: 2: 0 semi-planar
в–  YCbYCr 4: 2: 2
в–  CbYCrY 4: 2: 2 with alternation
в–  RGB444 and BGR444
в–  RGB555 and BGR555
в–  RGB565 and BGR565
в–  RGB888 and BRG888
в–  RGB101010 and BRG101010
в—Џ Image size from 96 Г— 96 to 1920 Г— 1088 (Full HD)
в—Џ Maximum frame rate up to 30 frames per second at a resolution of 1920 Г— 1080
в—Џ Supported data rate from 10 Kb / s to 20 Mb / s

♦ JPEG decoder
в—Џ Input JPEG file formats: YCbCr 4: 0: 0, 4: 2: 0, 4: 2: 2, 4: 4: 0, 4: 1: 1 and 4: 4: 4 samples
в—Џ RAW image output formats: YCbCr 4: 0: 0, 4: 2: 0, 4: 2: 2, 4: 4: 0, 4: 1: 1 and 4: 4: 4 semi-planar
в—Џ The size of the decoded image from 48 Г— 48 to 8176 Г— 8176 (66.8 megapixels)
в—Џ Maximum data rate up to 76 million pixels per second
♦ JPEG encoder
в—Џ Format of input RAW images:
в–  YCbCr 4: 2: 0 planar
в–  YCbCr 4: 2: 0 semi-planar
в–  YCbYCr 4: 2: 2
в–  CbYCrY 4: 2: 2 with alternation
в–  RGB444 and BGR444
в–  RGB555 and BGR555
в–  RGB565 and BGR565
в–  RGB888 and BRG888
в–  RGB101010 and BRG101010
в—Џ Output JPEG file: JFIF format version 1.02 or Non-progressive JPEG
в—Џ The size of the encoded image from 96Р§32 to 8192Р§8192 (67.1 Mp)
в—Џ Maximum data rate up to 90 million pixels per second

♦ Image Preprocessor
в—Џ Only used in conjunction with HD video encoder inside RK3066, does not support offline operation
в—Џ Converts RGB color space to YCbCr 4: 2: 0, compatible with BT.601, BT.709 or custom coefficients
в—Џ Provides YCbCr4: 2: 2 color space conversion to YCbCr4: 2: 0 color space
в—Џ Support for frame cropping operations from 8192Р§8192 to any size supported by the encoder
в—Џ Supports image rotation from 90 to 270 degrees
♦ Video stabilization
в—Џ Works in combined mode with HD video encoder inside RK3066 and offline
в—Џ Adaptive motion compensation filter
в—Џ Support scene detection from video stream and keyframe coding when scene change is noticed.
♦ Postprocessor images (built-in video decoder)
в—Џ Combined with an HD video decoder and a JPEG decoder, the postprocessor can receive data directly from the decoder output, to reduce the load on the data bus
в—Џ Also can work offline, input data can be from the interface with the camera or any other image data stored in external memory
в—Џ Input data formats:
в–  any format generated by the video decoder in the combined mode of operation
в–  YCbCr 4: 2: 0 semi-planar
в–  YCbCr 4: 2: 0 planar
в–  YCbYCr 4: 2: 2
в–  YCrYCb 4: 2: 2
в–  CbYCrY 4: 2: 2
в–  CrYCbY 4: 2: 2
в—Џ Output data formats:
в–  YCbCr 4: 2: 0 semi-planar
в–  YCbYCr 4: 2: 2
в–  YCrYCb 4: 2: 2
в–  CbYCrY 4: 2: 2
в–  CrYCbY 4: 2: 2
в–  Fully configurable ARGB channel lengths and locations in 32 bits, such as ARGB8888, RGB565, ARGB4444, etc.
в—Џ Input image size:
в–  In the combined mode: from 48 Г— 48 to 8176 Г— 8176 (66.8 megapixels)
в–  In offline mode: width from 48 to 8176, height from 48 to 8176, and the maximum size is limited to 16.7 megapixels
в–  16 pixel pitch
в—Џ Output image size: from 16 Г— 16 to 1920 Г— 1088 (horizontal pitch of 8 pixels, vertical pitch of 2 pixels)
в—Џ Support scaling zoom:
в–  Bicubic polynomial interpolation with a 4th order filter on the horizon and a 2nd order filter on the vertical
в–  Arbitrary scale factor separately for both dimensions, support for fractional coefficients
■ Maximum output image width — 3 times the enlarged input
в–  Maximum output image height - 3 times increased input
в—Џ Support scaling reduction:
в–  Arbitrary scale factor separately for both dimensions, support for fractional coefficients
в–  Unlimited scale reduction factor
в—Џ Provides YUV to RGB color space conversion compatible with BT.601-5, BT.709 or custom coefficients
в—Џ Blur support (2x2 ordered spatial blur, for 4,5.6-bit RGB channel accuracy)
в—Џ Programmable alpha channel support and alpha blend operation with the following input overlay formats:
в–  8 bits alpha + YUV444, big endian channel with AYUV8888
в–  8 bits alpha +24 bits RGB, big endian channel with ARGB8888
в—Џ Support for deinterlacing with conditional spatial deinterlace filtering, compatible only with the input format YUV420
в—Џ Support adjustment of contrast, brightness, color saturation of RGB image
в—Џ Supports image cropping and digital zoom only for JPEG or offline operation
в—Џ Picture-in-picture support
в—Џ Supports image rotation (horizontal reflection, vertical reflection, 90.180 or 270 degree rotation)
♦ Postprocessor images (standalone)
в—Џ Memory to memory mode
в—Џ Input data formats and sizes:
в–  RGB888: 16CH16 to 8191CH8191
в–  RGB565: 16CH16 to 8191CH8191
в–  YUV422 / YUV420: from 16Р§16 to 8190Р§8190
в–  YUV444: 16CH16 to 8190CH8190
в—Џ Pre-scaler:
в–  integer scale reduction factor (coefficients: 1 / 2,1 / 3,1 / 4,1 / 5,1 / 6,1 / 7,1 / 8) with a linear filter
в–  Deinterlacing (up to 1080i) to support YUV422 and YUV420 input formats
в—Џ Post Scaler:
в–  scale reduction with an arbitrary non-integer coefficient from 1/2 to 1
в–  scale increase with an arbitrary non-integer coefficient from 1 to 4
в–  4th order vertical and 2nd order horizontal filters
в–  Maximum width of the output image after the post-scaler is 4096 pixels
в—Џ Supports image rotation 90.180 or 270 degrees and X-reflection, Y-reflection

♦ 3D Graphics Engine
в—Џ Compatible with OpenGL ES1.1 and 2.0, OpenVG1.1
в—Џ Four built-in kernel shader
в—Џ Separation of vertex (geometric) and fragment (pixel) calculations for maximum parallel bandwidth
в—Џ Unified shader architecture
в—Џ Provides MMU and 128KB L2 Cache
в—Џ Triangle building speed: 30 M triangles / sec
в—Џ Pixel rendering speed: 1.4 GP / s
♦ 2D Graphics Engine
в—Џ Pixel rendering speed: 300 Mp / s without scaling, 150 Mp / s with bilinear scaling, 75 Mp / s with bicubic scaling
в—Џ Bit BLIT operations with support for BLIT stretching, simple BLIT and BLIT filter
в—Џ Color fill with gradient fill and pattern fill (pattern)
в—Џ Drawing lines with a smoothing filter and a certain width
в—Џ High-performance stretching and compressing
в—Џ Monochrome text rendering extension
в—Џ ROP2, ROP3, ROP4 full alpha blending and transparency
в—Џ Alpha blending modes, including the Porter-Duff Java 2 composition rules, color rearrangement, and pattern mask.
в—Џ 8K x 8K raster 2D coordinate system
в—Џ Rotate to any angles with smoothing on each 2D primitive
в—Џ Programmable bicubic filter to support image scaling
в—Џ Mixing, scaling and rotation are supported in one pass for BLIT stretch operations
в—Џ Source formats:
в–  ABGR8888, XBGR888, ARGB8888, XRGB888
в–  RGB888, RGB565
в–  RGBA5551, RGBA4444
в–  YUV420 planar, YUV420 semi-planar
в–  YUV422 planar, YUV422 semi-planar
в–  BPP8, BPP4, BPP2, BPP1
в—Џ Output formats:
в–  ABGR8888, XBGR888, ARGB8888, XRGB888
в–  RGB888, RGB565
в–  RGBA5551, RGBA4444
в–  YUV420 planar, YUV420 half-planar only in filtering and pre-scaling mode
в–  YUV422 planar, YUV422 half-planar only in filtering and pre-scaling mode

♦ Camera Interface
в—Џ 2 independent camera interface controllers
в—Џ Support up to 5 MP
в—Џ 8 bit CCIR656 (PAL / NTSC) interface
в—Џ 8 bit / 10 bit / 12 bit RAW interface
в—Џ YUV422 input format with YUV adjustable sequence
в—Џ YUV422, YUV420 output format with separate Y and UV space
в—Џ Picture-in-Picture (PIP) support
в—Џ Support for simple image effects such as sepia, negative, artistic freezing, relief, etc.
в—Џ Static histogram support statistics and white balance statistics
в—Џ Support for cropping an image under any size window
в—Џ Scaling support with arbitrary non-integer coefficient from 1/8 to 8
♦ Display Interface
в—Џ Two independent controller displays for HDMI and two TFT panel displays
в—Џ Support LCD TFT panels with resolution up to 1920 Г— 1080
в—Џ Support HDMI 1.4 output with 1080p @ 30fps resolution
в—Џ Supports TV interface with ITU-R BT.656 (8 bit, 480i / 576i / 1080i)
в—Џ Parallel RGB LCD interface: RGB888 (24 bit), RGB666 (18 bit), RGB565 (15 bit)
в—Џ Serial RGB LCD interface: 3 Г— 8 bits with support for RGB delta, 3 Г— 8 bits with the addition of dummy data, 16 bits complemented by 8 bits
в—Џ Microcontroller LCD interface: i8080 to 24-bit RGB
в—Џ 5 display layers:
в–  One background layer with programmable 24 bit color
в–  One video layer (win0)
в–є RGB888, ARGB888, RGB565, YUV422, YUV420, AYUV
в–є the maximum resolution is 1920 Г— 1080
в–є scaling engine with arbitrary non-integer coefficient in the interval from 1/8 to 8
в–є 256 levels of alpha blending
в–є Support for color key transparency
в–є Support 3D display
в–  One video layer (win1)
в–є RGB888, ARGB888, RGB565, YUV422, YUV420, AYUV
в–є the maximum resolution is 1920 Г— 1080
в–є scaling engine with arbitrary non-integer coefficient in the interval from 1/8 to 8
в–є 256 levels of alpha blending
в–є Support for color key transparency
в–  One OSD layer (win2)
в–є RGB888, ARGB888, RGB565, 1/2/4 / 8BPP
в–є 256 levels of alpha blending
в–є Support for color key transparency
в–  Hardware cursor (win3)
в–є 2 bit color
в–є maximum resolution 64 Г— 64
в–є 3-color and transparency mode
в–є 2-color + transparency + inverted mode
в–є 16 levels of alpha mix
в—Џ Supports 180 degree rotation in combined mode with LCD controller or separately
в—Џ 3 Г— 256 Г— 8 bits LUT display tables
в—Џ Win0 and Win1 layers may overlap with substitution
в—Џ Support color space conversion: YUV to RGB and RGB to YUV
в—Џ Support Deflicker (flicker suppression filter) for interlaced output
в—Џ Supports replication operations (16 bits to 24 bits) and blurring (24 bits to 16/18 bits)
♦ HDMI TX 1.4
в—Џ Compatible with HDMI version 1.4a, HDCP revision 1.4 and DVI version 1.0
в—Џ Supports digital TV (DTV) from 480i to 1080i / p HD resolution, and a PC with VGA to UXGA
в—Џ Supports 3D and 2048 Г— 4096 video resolution
в—Џ Programmable two-stream space converter
в—Џ Compatible with EIA / CEA-861D
в—Џ Supports color depths of up to 12 bits per pixel.
в—Џ xvYCC improved colorimetry
в—Џ Sending the Gamut Metadata package (Palette Metadata)
в—Џ Supports input digital video formats RGB, YCbCr including ITU.656
в—Џ 36 bits RGB / YCbCr 4: 4: 4, 16/20/24 bits YCbCr 4: 2: 2, 8/10 / 12bit YCbCr 4: 2: 2 (ITU.601 and 656)
в—Џ Standard SPDIF support for stereo or compressed audio up to 192 kHz
в—Џ Supports PCM, Dolby digital, DTS digital audio formats via four-bit I2S (up to 8 channels) compatible with IEC60958 or IEC61937
в—Џ Supports one-bit audio format (Super Audio CD)
в—Џ Support high bit rate audio formats
в—Џ Master I2C interface to connect to DDC (display data channel)
в—Џ Configuration registers are programmed through a parallel interface.
в—Џ Broad bandwidth, up to 2.2 Gb / s

♦ I2S / PCM 8 channel
в—Џ Up to 8 channels (4xTX, 4xRX)
в—Џ Audio data width from 16 bits to 32 bits
в—Џ Sampling frequency up to 192 kHz
в—Џ Provides master and slave operation modes, software configurable
в—Џ Supports 3 I2S formats (normal, left-handed alignment, right-handed alignment)
в—Џ Support 4 PCM formats (ahead, 1 late, 2 late, 3 late)
в—Џ I2S and PCM cannot be used simultaneously.
♦ I2S / PCM 2-channel
в—Џ 2 independent channels (2xTX, 2xRX)
в—Џ Audio data width from 16 bits to 32 bits
в—Џ Sampling frequency up to 192 kHz
в—Џ Provides master and slave operation modes, software configurable
в—Џ Supports 3 I2S formats (normal, left-handed alignment, right-handed alignment)
в—Џ Support 4 PCM formats (ahead, 1 late, 2 late, 3 late)
в—Џ I2S and PCM cannot be used simultaneously.
♦ SPDIF
в—Џ Audio data length: 16 bit / 20 bit / 24 bit
в—Џ Software configurable sampling rate (48 kHz, 44.1 kHz, 32 kHz)
в—Џ Stereo voice playback with two channels

♦ SDIO interface
в—Џ Compatible with SDIO 3.0 protocol
в—Џ Supports overflow and empty FIFO prevention by automatically stopping the card clock signal
в—Џ 4 bits data bus width
♦ High speed ADC & TS streaming interface
в—Џ Supports dual channel 8 bit / 10 bit interface
в—Џ Supports DMA and Interrupt Mode
в—Џ Support 8 bit streaming TS interface
в—Џ PID filter support:
в–  Combined with high-speed ADC interface to implement filtering of original TS data
в–  Provides PID filter up to 64 PID channels simultaneously
в–  Support for sync byte detection in the transport packet header
в–  Support for the detection of a lost packet under the condition of limited bandwidth
♦ MAC 10 / 100M Ethernet Controller
в—Џ Fully compliant with IEEE802.3u Ethernet Media Access Controller (MAC) standard
в—Џ Support 10 MB / s and 100 MB / s data transmission and reception speeds
в—Џ Auto-repeat and automatic removal of the collision frame
в—Џ Support full duplex
в—Џ Support full-duplex flow control with PAUSE frame
в—Џ Address filtering (broadcast, multicast, logical, physical)
в—Џ Support only RMII mode
в—Џ In RMII mode, the clock frequency can be from RK3066 or from an external Ethernet PHY controller
♦ SPI controller
в—Џ 2 channels
в—Џ Support for software configurable Master and Slave modes
в—Џ Supports DMA or Interrupt Mode
в—Џ Two built-in 32-by-16-bit FIFOs for TX and RX operations, respectively
в—Џ Supports 2 chip select selects in Master mode
♦ UART controller
в—Џ 4 channels
в—Џ Supports DMA or Interrupt Mode
в—Џ For UART1 / UART2 / UART3 two built-in FIFOs of 32B for TX and RX operations, respectively
в—Џ For UART0 two built-in FIFOs of 64B for TX and RX operations, respectively
в—Џ Support 5 bits, 6 bits, 7 bits and 8 bits of bit data for reception and transmission
в—Џ Standard service bits for asynchronous channels, such as start, stop and parity
в—Џ Supports various input frequency sources for the UART controller to achieve data transmission / reception speeds of up to 4 Mbaud or other special speeds.
в—Џ Support for non-integer clock dividers for generating data transmission and reception speeds
в—Џ Automatic flow control mode is provided only for UART0, UART1, UART2
♦ I2C controller
в—Џ 5 channels
в—Џ Support Multi-master operation mode
в—Џ Supports 7-bit and 10-bit addressing
● Software settable data transmission and reception frequency, up to 400 Kb / s in “fast” mode
● Serial 8-bit and bi-directional data transmissions can be performed at a speed of 100 Kb / s in the “standard” mode
♦ GPIO (General Purpose Input / Output - general purpose input / output ports)
в—Џ 6 GPIO port groups (GPIO0 ~ GPIO4, GPIO6), 32 GPIO ports per GPIO0 ~ GPIO4 group, and 16 ports on GPIO6, a total of 176 GPIO ports
в—Џ All GPIO ports can be used to generate interrupts to Cortex-A9 cores
● GPIO6 ports can be used to “wake up” the system from the stop, sleep or power saving mode
в—Џ A pull-up resistor to the power supply (pull-up) or to the ground (pull-down) can be programmatically connected to all GPIO ports.
в—Џ All ports are pulled by default to power or ground except for GPIO15 (PWM 3)
в—Џ All GPIO ports after power on are in input mode - default mode
♦ USB Host2.0
в—Џ Compatible with USB Host2.0 specification
в—Џ Mode support: high-speed (480 MB / s), full-speed (12 MB / s) and low-speed (1.5 MB / s)
в—Џ Provides 16 channels in Host mode
в—Џ Support cyclic transfers in host mode
♦ USB OTG2.0
в—Џ Compatible with USB OTG2.0 specification
в—Џ Support high-speed (480Mb / s), full-speed (12Mb / s) and low-speed (1.5Mb / s) modes
● Supports up to 9 endpoints in “Device” mode, in addition to end point 0
в—Џ Supports up to 6 input endpoints in Device mode, including end point 0
в—Џ End points 1/3/5/7 can only be used as input end points.
в—Џ Endpoints 2/4/6 can only be used as output endpoints.
в—Џ End points 8/9 can be used as input and output end points
● Provides up to 9 channels in “Host” mode

♦ Temperature sensor
в—Џ 2 sensors based on bipolar transistors
в—Џ 2 channels of 12-bit sequential approximation ADC (SAR ADC)
в—Џ Temperature measurement error В± 5 degrees
♦ sequential approximation ADC (SAR-ADC)
в—Џ Four 10-bit channels
в—Џ Conversion speed varies from 0.1 to 1 Msps (sps - sample per second)
в—Џ The frequency of the input signal of the ADC should not exceed 1 MHz
в—Џ DNL (differential nonlinearity) is less than В± 1 LSB, INL (integral nonlinearity) is less than В± 2.0 LSB
в—Џ Current in power saving mode no more than 0.5 ВµA for analog and digital logic
в—Џ Analog interface power 2.5 V (В± 10%)
♦ eFuse
в—Џ 256 bits (32 Г— 8) high density electronic fuse
в—Џ Programming conditions: VDDQ should be 2.5 V (В± 10%)
в—Џ Programming time about 4 ~ 6 Вµs
в—Џ Reading conditions: VDDQ must be 0 V or cast.
в—Џ Supports power saving and standby mode
♦ Power supply range
в—Џ 1.1 V core power (В± 10%)
в—Џ Power supply of 3.3V, 2.5V or 1.8V I / O lines and interfaces (В± 10%)
♦ Technological process
в—Џ TSMC 40 nm LP
♦ Enclosure type
в—Џ TFBGA453LD 19 mm x 19 mm (ball size 0.4 mm; ball pitch 0.8 mm)